Modern integrated circuits are constructed with up to several million active devices, such as transistors and capacitors, formed in and on a semiconductor substrate. Interconnections between the active devices are created by providing a plurality of conductive interconnection layers, such as polycrystalline silicon and metal, which are etched to form conductors for carrying signals. The conductive layers and interlayer dielectrics are deposited on the silicon substrate wafer in succession, with each layer being, for example, on the order of 1 micron in thickness.
A common intermediate structure for constructing integrated circuits is the stack structure. FIG. 1 illustrates the stack structure and the typical process for forming it. The process begins with structure 10, which has a silicon substrate 12 supporting one or more layers of gate materials, shown collectively as 14. The gate materials may include a variety of layers including oxides, polycrystalline silicon (polysilicon) or polycrystalline silicon-germanium, metals such as tungsten, and nitrides such as titanium nitride. Above the gate layer is a hard mask layer 16, which may also include a variety of layers including nitrides, anti-reflective coatings (ARC), oxides, and silicides. Finally, a resist material 18 is present on top of the structure. Here the resist layer has been patterned, for example by standard lithographic techniques.
Referring still to FIG. 1, etching of the hard mask layer 16 in the regions not covered by the resist material 18 allows for the formation a patterned hard mask 22 as illustrated in structure 20. The resist may then be stripped to yield structure 30, which has patterned hard mask 22 as the only masking layer. The patterned hard mask protects the underlying gate materials during the processing of the exposed portions of the gate materials. This processing may include steps such as etching, to yield structure 40 with a patterned gate layer 42. The processing may also include depositing, oxidation and ion implantation to form functional elements within the structure, such as gates, source/drain regions, contacts, isolation areas and vias.
There is an ongoing need to reduce the size of the elements within integrated circuits and semiconductor structures. The smallest width of any element in a semiconductor device is typically referred to as the critical dimension (CD) of the device. Two conventional methods for reducing the CD, and therefore reducing the width of the gate structures, are resolution enhancement and dry etching. Resolution enhancement can reduce the CD of the resist pattern, thus providing for a smaller CD in the subsequent etch processes. Although this method can provide very small CD's with good CD control, it requires the use of special photolithography equipment which may be very expensive. Dry etching can reduce the CD by exposing a patterned hard mask to prolonged dry etch conditions. Thus, the side walls of the hard mask are eroded by the etching. This method requires an increase in the amount of resist material, since the resist is present during the prolonged dry etch in order to protect the top of the hard mask. Also, the dry etch method has poor control over the reproducibility of the final CD obtained.